1. Technical Field
The present disclosure relates to a source driver and more particularly, to an apparatus and method for driving image data which reduces a peak current.
2. Discussion of the Related Art
A conventional display device may include a source driver, a gate driver, and a pixel array. When digital image data is displayed or stored in the pixel array of the display device, the gate driver sequentially drives a plurality of gate lines and the source driver displays or stores the digital image data in pixels of the pixel array connected to a driven gate line.
FIG. 1 is a block diagram of a conventional source driver 10. Referring to FIG. 1, the source driver 10 includes a shift register block 20, a sampling memory block 30, a hold memory block 40, a level shifting block 50, a digital-to-analog converter (DAC) block 60, a grayscale voltage generation unit 65, and an output buffer block 70.
The shift register block 20 shifts a start pulse signal SP input from a controller (not shown) in response to a clock signal CLK. The sampling memory block 30 samples digital image data R/G/B input from the controller in response to signals S1 through Sn (where n is an integer) output from the shift register block 20. The hold memory block 40 stores the sampled digital image data R/G/B for a horizontal scan time.
The hold memory block 40 is driven at a low voltage, for example, 0.6V-3.3V, and the DAC block 60 and the output buffer block 70 are driven at a high voltage, for example, 3.8V-18V. The level shifting block 50 changes the voltage level of the digital image data R/G/B stored in the hold memory 40 and provides digital image data RIG/B with a changed voltage level to the DAC block 60.
The DAC block 60 outputs a voltage from a plurality of grayscale voltages V0-Vz (where z is an integer) generated from the grayscale voltage generation unit 65 to the output buffer block 70 based on the digital image data with the changed voltage level. The output buffer block 70 outputs the voltage output from the DAC block 60 to channels CH1 through CHn.
FIG. 2 is a block diagram 200 of a single channel for 6 bit digital image data R/G/B of the source driver 10 shown in FIG. 1. Referring to FIG. 2, the hold memory block 40 includes six latches 211 through 216 for storing the 6 bit digital image data signal R/G/B sampled by the sampling memory block 30. The level shifting block 50 includes six level shifters 221 through 226 for performing level shifting of an output voltage of each of the latches 211 through 216.
The DAC block 60 selects and outputs one of the grayscale voltages V0-Vz (z=63) of 64 levels based on the outputs of the six level shifters 221 through 226. The DAC block 60 can be embodied by a binary search DAC having 128 transistors. Each of the level shifters 221 through 226 can be embodied by using differential amplifiers. Bit data D1 and inverted bit data DB1 of the digital image data is input to input terminals of the differential amplifiers.
FIG. 3 is a circuit diagram of the level shifter 221 of FIG. 2. Referring to FIG. 3, the bit data D1 and inverted bit data DB1 of the digital image data is input to the level shifter 221. The level of the bit data D1 may transition. For example, the bit data D1 of the digital image data can be transitioned from bit data “0” of a second logic level to bit data “1” of a first logic level.
As soon as the transition occurs, transistors T1, T2, and T3 of the level shifter 221 can be simultaneously turned on. A peak current can be generated between a supply voltage VDD and a ground voltage VSS of the level shifter 221.
The source driver 10 outputs the 6 bit digital image data D1 through D6 to the six level shifters 221 through 226 of FIG. 2 while the six level shifters 221 through 226 are all operated. Thus, peak currents corresponding to the six level shifters 221 through 226 per channel of the source driver 10 can be generated.
Since a high voltage for example, a VDD of 18V, is used for the operation of the level shifters 221 through 226, a large amount of power may be consumed due to the peak current. Therefore, it is necessary to reduce the peak current in the source driver.